1. Field of the Invention
The present invention relates to SRAM memory.
2. Description of Related Art
FIG. 1 is a circuit diagram for illustrating the structure of a memory cell in a conventional SRAM (static random access memory). In the figure, the SRAM memory cell comprises a pair of selector transistors 1 and 2, a pair of driver transistors 3 and 4 cross-connected from drains to gates of each other, and a pair of pull-up elements 5 and 6 connected to the drains of the driver transistors 3 and 4. For the pull-up elements 5 and 6, load resistances or PMOS's (p-type metal oxide film semiconductors) are used.
Recently, the above-mentioned conventional SRAM memory cell has been modified in structure; that is, the pull-up elements 5 and 6 made of polycrystal silicon are laminated on the selector transistors 1 and 2, and driver transistors 3 and 4. By applying this technique, the area of the memory cell can be reduced. However, the above-mentioned structure is disadvantageous because a number of processes for manufacturing increases, and in addition, metal processing on the top layer becomes difficult due to a complex structure of the laminate and step gaps on the memory cell.
Diffusion of an impurity is very fast in polycrystal silicon, when the designed size is small, in that the impurity diffuses from both the ends of a resistance, and the impurity can make the thin film transistor (TFT) of resistance or PMOS conductive. The size of the memory cell cannot therefore be minimized due to the restriction arising from the diffusion of the impurity. This is another disadvantage.